1. Technical Field of the Invention
The present invention relates to an improved Content Addressable Memory (CAM) cell architecture.
2. Description of Related Art
Content Addressable Memory (CAM) gets its name from the fact that a data word is selected or identified by its contents rather than by its physical address. In other words, a CAM is a memory that can be instructed to compare a specific pattern of comparand or reference data with data stored in the CAM array. The entire CAM array is searched in parallel for a match with the comparand data. CAMs are used in a variety of applications, such as sorting large databases, pattern-matching for image processing and voice recognition and cache systems of high speed computing systems. CAM cells are becoming increasingly popular in high-speed network routers and many other applications known in the art of computing.
A standard content addressable memory comprises an array of individual CAM cells. Each CAM cell consists of a data storage unit and comparison circuitry. A CAM cell can store a single bit of data and can compare the stored bit with a comparand or reference bit during a search operation.
In a common implementation, each row represents a different word of maximum length equal to the total number of columns in the CAM array. During the comparison operation, if all the reference bits match the corresponding stored data bits, a match is deemed to be achieved otherwise the match operation is failed. An indicator, commonly known as a Match Line (ML), associated with each stored word indicates a match or mismatch, which can be detected by a sense amplifier or any other sensing means connected to each ML.
To compare and combine the results of multiple cells of a row several approaches are used one of which is a NAND configuration, wherein the ML driver devices (pass transistors) of all the cells belonging to a word are connected in series. This NAND configuration consumes less power but is inherently slower than desired for CAMs used in modern deep-sub micron processes where supply voltage is continually decreasing.
In another common implementation, a NOR configuration is used for high-speed CAMs, wherein the ML driver devices (pass transistors) of all the cells belonging to a word are connected in parallel to pull down an initially precharged (at logical “High”) ML during the SEARCH operation. With this NOR configuration, a match for a word occurs whenever no cell of the row drives ML “low”. This NOR configuration is faster than a NAND configuration but consumes considerably larger power.
Throughout this disclosure, logical “1” refers to and is interchangeable with a logical “High” corresponding to a voltage VDD, while logical “0” refers to and is interchangeable with a logical “Low” corresponding to GND. FIG. 1 illustrates a prior art 9-transistor CAM cell 100 with NOR configuration. The CAM cell 100 includes an SRAM cell for data storage, comprising a pair of cross-coupled inverters formed by transistors 111, 112, 113 and 114 and a pair of access transistors 115 and 116. The comparison circuitry of the CAM cell 100 comprises a pair of pass transistors 117 and 118. The conducting terminals of the pass transistor 113 and 111 are connected in series between the supply voltage VDD and ground GND while the control terminals are connected to the common conducting terminals F of the pass transistors 114 and 112. The conducting terminals of the pass transistor 114 and 112 are also connected in series between VDD and GND while the control terminals are connected to the common conducting terminals T of the pass transistors 113 and 111. The conducting terminals of pass transistors 115 and 116 connect nodes T and F to the corresponding bit lines BLT and BLF while the control terminals are connected to word line WL. The pass transistors 117 and 118 are connected in series between bit lines BLT and BLF and the common node is labeled as the Bit-Match node. The control terminals of transistors 117 and 118 are coupled to nodes F and T, respectively. Pass transistor 119 is coupled between ML and ground GND and its control terminal is connected to the Bit-Match node of the CAM cell.
The READ and WRITE operations of this CAM cell 100 are the same as those of a standard 6-transistor SRAM cell, wherein the precharge state of bit lines BLT and BLF is logical “High”. During the SEARCH operation, bit lines BLT and BLF are initially precharged to logical “Low” and ML is precharged to logical “High”. Then the comparand bit is placed on BLT and its complement is placed on BLF. If the comparand bit matches with the data bit stored in the CAM cell, then one of the pass transistors 117 or 118 drives the Bit-Match node to logical “0” and therefore ML remains at logical “High”, indicating a match. On the other hand, if there is a mismatch between the applied comparand bit and the data bit stored in the CAM cell, then one of the pass transistors 117 or 118 drives the Bit-Match node to “VDD−Vtn”, thereby turning the pull-down transistor 119 on and pulling down ML indicating a mismatch.
The CAM cell 100 requires a precharge to logical “Low” operation for bit lines and a precharge to logical “High” operation for ML when a SEARCH operation is requested if the default standby state is for a READ or a WRITE operation. Conversely, if the CAM cell 100 is ready for a SEARCH operation in its default standby state, then the bit lines must be precharged to logical “High” and ML is thereby discharged when a READ or WRITE operation is requested. It is known that both bit lines and ML impose a heavy capacitive load on their drivers and prechargers. Therefore, CAM cell 100 consumes more power and provides larger READ/WRITE/SEARCH access times.
FIG. 2 illustrates another prior art 9-transistor CAM cell 200 using a NOR configuration, wherein the only difference between the CAM cell 100 and 200 is that the CAM cell 200 is provided with dedicated lines CBLT and CBLF for the search operation as shown in the figure. Thus, CAM cell 200 provides more flexibility in the timing of READ, WRITE and SEARCH operations but at the cost of hardware overhead required for controlling the dedicated compare bit lines CBLT and CBLF.
FIG. 3 illustrates another prior art 9-transistor CAM cell 300 with NOR configuration in accordance with U.S. Pat. No. 5,446,685 using pulsed ground technique to reduce the power consumption in comparison to conventional NOR configured CAM cells. The pull-down device to drive the ML to a logical “Low” during a mismatch is a pass transistor 319. The pass transistor 319 is connected between ML and a Search Enable Line and its gate is connected to the Bit-Match node. The Search Enable Line pulsed to ground only during the SEARCH operation. The CAM cell 300 has a single standby state for READ, WRITE and SEARCH operations, leading to higher speed operations by eliminating precharge operations at the start of the cycles and to lower power consumption because there is no standby state change between READ/WRITE and. SEARCH operations.
There are however, a number of disadvantages associated with CAM cell 300. These disadvantages can be explained by describing the SEARCH access cycle. Suppose a CAM cell stores a logical “0”, that is, node T is at logical “0” and node F is at logical “1”. In the standby state, bit lines BLT and BLF, Search Enable Line and ML will be precharged to logical “1”. Since the control terminal of the pass transistor 317 is connected to node F, which is at logical “1”, therefore the transistor 317 will be ON and will drive the Bit-Match node to voltage “VDD−Vtn”. On the other hand, the pass transistor 318 will be OFF as its gate is connected to node T that is at logical “0”. When a SEARCH is requested, the comparand bit and its complementary bit are placed on bit lines BLT and BLF respectively. Simultaneously, the Search Enable Line is provided a pulsed ground. Now, due to bootstrapping, the gate-to-source capacitance (Cgs) of the pull-down transistor 319 tends to decrease the voltage at Bit-Match node as the Search Enable Line rapidly switches from logical “High” to logical “Low”. Consequently one of the following two cases can occur:
In the first case, the comparand bit matches the stored data bit, that is BLT and node T are at the same logic state and similarly, BLF and node F are at the complement of the logical state. One of the pass transistors 317 or 318 (317 in this case as node F is at logical “1”) drives the Bit-Match node to full logical “0” and therefore ML remains at logical “High” indicating that a match has been detected.
In the second case, there is a mismatch between the comparand bit and stored data bit, that is BLT and node T are at opposing logical values. One of the transistors 317 or 318 (317 in this case as node F is at logical “1”) drives the Bit-Match node to “VDD−Vtn”, thereby turning ON the pass transistor 319. Thus, pass transistor 319 begins to pull-down the ML, indicating a mismatch. In the mismatch condition, the Bit-Match node initially observes a downward spike due to bootstrapping, described above, before settling at “VDD−Vtn” as it is being driven by one of the pass transistors 317 or 318. Thus, in the mismatch condition, the voltage at the Bit-Match node remains essentially less than “VDD−Vtn” and hence, discharging of ML through the pass transistor 319 is slower than what is expected if the Bit-Match node were at VDD. Since the search access time in a NOR-configured CAM cell is mainly determined by the discharge of ML (No discharge of ML in match condition, which is same as the precharge state of ML), therefore search access time is large in this type of implementation. Moreover, as the supply voltages being utilized are decreasing in current designs, a slight change in voltage can significantly affect the performance of a device.
As soon as the SEARCH operation is over, bit lines BLT and BLF, Search Enable Line and ML return to the respective standby states (logical “High” for all). As the Search Enable Line rapidly switches from logical “Low” to logical “High”, it causes the bootstrapping to occur again at Bit-Match node, this time in the opposite direction. This results in two cases:
In the first case, if there was a match during the SEARCH operation, then the voltage at Bit-Match node is “0”, after the SEARCH operation rises only up to its standby state value of “VDD−Vtn”.
In the second case, if there was a mismatch during the SEARCH operation, the voltage at the Bit-Match node would be “VDD−Vtn”. Furthermore, this voltage “VDD−Vtn” rises beyond VDD due to the bootstrapping after the SEARCH operation. In fact, the voltage at Bit-Match node reaches a value of “(2VDD)−Vtn” and remains at this value until the next SEARCH cycle starts because both the pass transistors 317 and 318 become OFF. Thus, until the next SEARCH cycle starts, the pass transistor 317 has terminal voltages “VDD” and “(2VDD)−Vtn” with the gate at “VDD” (voltage at node F) and similarly the pass transistor 318 has terminal voltages “VDD” and “(2VDD)−Vtn” with the gate at “0” (voltage at node T). Thus, the drain-to-gate voltage of the pass transistor 318 is at “(2VDD)−Vtn” and the voltage across the reverse biased drain-to-substrate diode is at “(2VDD)−Vtn”, which could degrade the device. A similar situation occurs with the pass transistor 317 in a cell in which node T is at logical “1” and node F is at logical “0” and a mismatch occurs in that cell. This logical “High” voltage (which is greater than a normal full logical “High”) at the gate of the pull-down transistor 319 degrades the gate-oxide. If the mismatch spreads over several SEARCH cycles, which normally happens in CAM arrays, the bootstrapping becomes a severe problem.
The bootstrapping that occurs within each CAM cell at the Bit-Match node slows the discharging of ML and hence reduces the speed of SEARCH operation and also results in higher than normal degradation rates of the transistors involved. The above problems with the bootstrapping become increasingly significant in sub-micron technologies.
These limitations highlight the need for a CAM cell implementation that offers faster SEARCH operation at lower power consumption and improves reliability.